The present invention is directed towards an I/O buffer of an integrated circuit and, more particularly, to an I/O buffer that can handle multiple voltage levels.
The integrated circuit industry is continually driven to reduce costs, reduce power consumption, and improve performance. Price reduction is strongly driven by migrating products to smaller and smaller sizes, which reduce die size and increase yields. As a result, the continual scaling and shrinking of device geometries, device sizes and dimensions require that the operating voltages be similarly scaled. Operating voltages have been scaled down from 5 volts to 3.3 volts and, now, down to 1.8 volts and 1.3 volts. This has resulted in the need for mixed voltage mode systems. In other words, integrated circuits will need to interface with other integrated circuits that operate at various voltages. However, this means that the interface circuitry, typically an I/O buffer, must be able to withstand voltages that range from 1.3 volts to 5 volts.
With the scaling down of the device sizes, the transistor length and gate oxide thickness is now much smaller, thereby being more suitably adapted for low-voltage applications. However, when a high voltage is applied to such devices, the high voltages can produce an undesirable amount of stress, causing breakdown of the transistor device.
Further, many integrated circuits are now used in applications where power consumption is of great concern. Thus, the I/O circuit should protect from high voltages and have little, if any, power consumption.